The NEURAghe architecture has proved to be a powerful accelerator for deep convolutional neural networks running on heterogeneous architectures based on Xilinx Zynq-7000 all programmable system-on-chips. NEURAghe exploits the processing system and the programmable logic available in these devices to improve performance through parallelism, and to widen the scope of use-cases that can be supported. In this letter, we extend the NEURAghe template-based architecture to guarantee design-time scalability to multiprocessor SoCs with vastly different cost, size, and power envelope, such as Xilinx's Z-7007s, Z-7020, and Z-7045. The proposed architecture achieves state-of-the-art performance and cost effectiveness in all the analyzed configurations, reaching up to 335 GOps/s on the Z-7045.

Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge / Meloni, P.; Loi, D.; Deriu, G.; Carreras, M.; Conti, F.; Capotondi, A.; Rossi, D.. - In: IEEE EMBEDDED SYSTEMS LETTERS. - ISSN 1943-0663. - 12:2(2020), pp. 62-65. [10.1109/LES.2019.2947312]

Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge

Capotondi A.
;
2020

Abstract

The NEURAghe architecture has proved to be a powerful accelerator for deep convolutional neural networks running on heterogeneous architectures based on Xilinx Zynq-7000 all programmable system-on-chips. NEURAghe exploits the processing system and the programmable logic available in these devices to improve performance through parallelism, and to widen the scope of use-cases that can be supported. In this letter, we extend the NEURAghe template-based architecture to guarantee design-time scalability to multiprocessor SoCs with vastly different cost, size, and power envelope, such as Xilinx's Z-7007s, Z-7020, and Z-7045. The proposed architecture achieves state-of-the-art performance and cost effectiveness in all the analyzed configurations, reaching up to 335 GOps/s on the Z-7045.
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Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge / Meloni, P.; Loi, D.; Deriu, G.; Carreras, M.; Conti, F.; Capotondi, A.; Rossi, D.. - In: IEEE EMBEDDED SYSTEMS LETTERS. - ISSN 1943-0663. - 12:2(2020), pp. 62-65. [10.1109/LES.2019.2947312]
Meloni, P.; Loi, D.; Deriu, G.; Carreras, M.; Conti, F.; Capotondi, A.; Rossi, D.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11380/1227270
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