本发明涉及常关断型HEMT晶体管以及对应的制造方法。一种常关断型HEMT晶体管包括:半导体异质结(4、6、200),其至少包括一个第一层(4)和一个第二层(6),第二层布置在第一层的顶部上;沟槽(15),其延伸穿过第二层和第一层的一部分;导电材料的栅极区(10),其在沟槽中延伸;以及介电区(18),其在沟槽中延伸,涂覆栅极区并且接触半导体异质结。沟槽的一部分由形成至少一个第一台阶(Pb1、Pl1、Pb2)的横向结构(LS)横向定界。半导体异质结形成第一台阶的第一边缘(E1)和第二边缘(E2),第一边缘由第一层形成。

The invention relates to an HEMT transistor of the normally off type and a corresponding manufacturing method. The HEMT transistor of the normally off type, including: a semiconductor heterostructure (4, 6, 200), which comprises at least one first layer (4) and one second layer (6), the second layer being set on top of the first layer; a trench (15), which extends through the second layer and a portion of the first layer; a gate region (10) of conductive material, which extends in the trench; and a dielectric region (18), which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure (LS) that forms at least one first step (Pb1, Pl1, Pb2). The semiconductor heterostructure forms a first edge (E1) and a second edge (E2) of the first step, the first edge being formed by the first layer.

常关断型hemt晶体管以及对应的制造方法 / Iucolano, Ferdinando; Patti, Alfonso; Chini, Alessandro. - (2016 May 26).

常关断型hemt晶体管以及对应的制造方法

Alessandro Chini
2016

Abstract

The invention relates to an HEMT transistor of the normally off type and a corresponding manufacturing method. The HEMT transistor of the normally off type, including: a semiconductor heterostructure (4, 6, 200), which comprises at least one first layer (4) and one second layer (6), the second layer being set on top of the first layer; a trench (15), which extends through the second layer and a portion of the first layer; a gate region (10) of conductive material, which extends in the trench; and a dielectric region (18), which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure (LS) that forms at least one first step (Pb1, Pl1, Pb2). The semiconductor heterostructure forms a first edge (E1) and a second edge (E2) of the first step, the first edge being formed by the first layer.
26-mag-2016
STMicroelectronics SRL
CN106711039A
Internazionale
Iucolano, Ferdinando; Patti, Alfonso; Chini, Alessandro
File in questo prodotto:
File Dimensione Formato  
CN106711039A.pdf

Open access

Tipologia: Versione pubblicata dall'editore
Dimensione 909.22 kB
Formato Adobe PDF
909.22 kB Adobe PDF Visualizza/Apri
Pubblicazioni consigliate

Licenza Creative Commons
I metadati presenti in IRIS UNIMORE sono rilasciati con licenza Creative Commons CC0 1.0 Universal, mentre i file delle pubblicazioni sono rilasciati con licenza Attribuzione 4.0 Internazionale (CC BY 4.0), salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1190112
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus ND
  • ???jsp.display-item.citation.isi??? ND
social impact