Hierarchical scheduling is an effeective approach developed to support the integration of independently developed ap- plications on the same computing platform. In particular, the M-BROE framework has been recently proposed and analyzed to efficiently support component-based development on multiprocessor platforms through the virtual multiprocessor abstraction implemented by reservation servers, in the presence of shared resources. However, the problems of partitioning applications to virtual processors and defining reservation parameters were not addressed. This paper fills this gap by proposing a design methodology as an optimization problem for partitioning applications to virtual processors, performing a synthesis of the component interface and allocating virtual processors to physical processors. Experimental results are also presented to evaluate the proposed methodology.
Partitioning and Interface Synthesis in Hierarchical Multiprocessor Real-Time Systems / Biondi, Alessandro; Buttazzo, Giorgio; Bertogna, Marko. - 19-21-:(2016), pp. 257-266. (Intervento presentato al convegno 24th International Conference on Real-Time Networks and Systems, RTNS 2016 tenutosi a Brest, France nel October 2016) [10.1145/2997465.2997489].
Partitioning and Interface Synthesis in Hierarchical Multiprocessor Real-Time Systems
BERTOGNA, Marko
2016
Abstract
Hierarchical scheduling is an effeective approach developed to support the integration of independently developed ap- plications on the same computing platform. In particular, the M-BROE framework has been recently proposed and analyzed to efficiently support component-based development on multiprocessor platforms through the virtual multiprocessor abstraction implemented by reservation servers, in the presence of shared resources. However, the problems of partitioning applications to virtual processors and defining reservation parameters were not addressed. This paper fills this gap by proposing a design methodology as an optimization problem for partitioning applications to virtual processors, performing a synthesis of the component interface and allocating virtual processors to physical processors. Experimental results are also presented to evaluate the proposed methodology.File | Dimensione | Formato | |
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