A major obstacle towards the adoption of multi-core platforms for real-time systems is given by the difficulties in characterizing the interference due to memory contention. The simple fact that multiple cores may simultaneously access shared memory and communication resources introduces a significant pessimism in the timing and schedulability analysis. To counter this problem, predictable execution models have been proposed splitting task executions into two consecutive phases: a memory phase in which the required instruction and data are pre-fetched to local memory (M-phase), and an execution phase in which the task is executed with no memory contention (C-phase). Decoupling memory and execution phases not only simplifies the timing analysis, but it also allows a more efficient (and predictable) pipelining of memory and execution phases through proper co-scheduling algorithms. In this paper, we take a further step towards the design of smart co-scheduling algorithms for sporadic real-time tasks complying with the M/C (memory-computation) model. We provide a theoretical framework that aims at tightly characterizing the schedulability improvement obtainable with the adopted M/C task model on a single-core systems. We identify a tight critical instant for M/C tasks scheduled with fixed priority, providing an exact response-time analysis with pseudo-polynomial complexity. We show in our experiments that a significant schedulability improvement may be obtained with respect to classic execution models, placing an important building block towards the design of more efficient partitioned multi-core systems.

Memory-processor co-scheduling in fixed priority systems / Melani, Alessandra; Bertogna, Marko; Bonifaci, Vincenzo; Marchetti Spaccamela, Alberto; Buttazzo, Giorgio. - (2015), pp. 87-96. ((Intervento presentato al convegno 23rd International Conference on Real-Time Networks and Systems, RTNS 2015 tenutosi a Lille France nel 4-6 Novembre 2015 [10.1145/2834848.2834854].

Memory-processor co-scheduling in fixed priority systems

BERTOGNA, Marko;
2015-01-01

Abstract

A major obstacle towards the adoption of multi-core platforms for real-time systems is given by the difficulties in characterizing the interference due to memory contention. The simple fact that multiple cores may simultaneously access shared memory and communication resources introduces a significant pessimism in the timing and schedulability analysis. To counter this problem, predictable execution models have been proposed splitting task executions into two consecutive phases: a memory phase in which the required instruction and data are pre-fetched to local memory (M-phase), and an execution phase in which the task is executed with no memory contention (C-phase). Decoupling memory and execution phases not only simplifies the timing analysis, but it also allows a more efficient (and predictable) pipelining of memory and execution phases through proper co-scheduling algorithms. In this paper, we take a further step towards the design of smart co-scheduling algorithms for sporadic real-time tasks complying with the M/C (memory-computation) model. We provide a theoretical framework that aims at tightly characterizing the schedulability improvement obtainable with the adopted M/C task model on a single-core systems. We identify a tight critical instant for M/C tasks scheduled with fixed priority, providing an exact response-time analysis with pseudo-polynomial complexity. We show in our experiments that a significant schedulability improvement may be obtained with respect to classic execution models, placing an important building block towards the design of more efficient partitioned multi-core systems.
23rd International Conference on Real-Time Networks and Systems, RTNS 2015
Lille France
4-6 Novembre 2015
87
96
Melani, Alessandra; Bertogna, Marko; Bonifaci, Vincenzo; Marchetti Spaccamela, Alberto; Buttazzo, Giorgio
Memory-processor co-scheduling in fixed priority systems / Melani, Alessandra; Bertogna, Marko; Bonifaci, Vincenzo; Marchetti Spaccamela, Alberto; Buttazzo, Giorgio. - (2015), pp. 87-96. ((Intervento presentato al convegno 23rd International Conference on Real-Time Networks and Systems, RTNS 2015 tenutosi a Lille France nel 4-6 Novembre 2015 [10.1145/2834848.2834854].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1118717
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