Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes
2018 Dazzi, Martino; Palestri, Pierpaolo; Rossi, Davide; Bandiziol, Andrea; Loi, Igor; Bellasi, David; Benini, Luca
Effect of the Grid Size on the Stability of Self-Consistent Monte-Carlo Simulations
2005 N., Barin; Palestri, Pierpaolo; Esseni, David; C., Fiegna
Monte-Carlo simulation of MOSFETs with Band-Offsets in the Source and Drain
2007 Braccioli, M; Palestri, Pierpaolo; Poiroux, T; Vinet, M; Le Carval, G; Mouis, M; Fiegna, C; Sangiorgi, E; Deleonibus, S.
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers
2019 D'Ampolo, Dylan; Bandiziol, Andrea; Menin, Davide; Grollitsch, Werner; Nonis, Roberto; Palestri, Pierpaolo
Investigation on convergence and stability of self-consistent Monte Carlo device simulations
2002 Clerc, R; Palestri, Pierpaolo; Abramo, Antonio
Hot Carrier Degradation: From Defect Creation Modeling to Their Impact on NMOS Parameters
2012 Mamy Randriamihaja, Y; Zaka, A; Huard, V; Rafik, M; Rideau, D; Roy, D; Bravaix, A; Palestri, Pierpaolo
A New Model for the Backscatter Coefficient in Nanoscale MOSFETs
2010 J. L. P. J., Van Der Steen; Palestri, Pierpaolo; Esseni, David; R. J. E., Hueting
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm
2018 Bandiziol, Andrea; Grollitsch, Werner; Brandonisio, Francesco; Bassi, Matteo; Nonis, Roberto; Palestri, Pierpaolo
Mobility in high-K metal gate UTBB-FDSOI devices: From NEGF to TCAD perspectives
2013 D., Rideau; Y. M., Niquet; Nier, Oliver; A., Cros; J. P., Manceau; Palestri, Pierpaolo; Esseni, David; V. H., Nguyen; F., Triozon; J. C., Barbe; I., Duchemin; D., Garetto; L., Smith; L., Silvestri; F., Nallet; R., Clerc; O., Weber; F., Andrieu; E., Josse; C., Tavernier; H., Jaouen
Package Design Methodology for Crosstalk Mitigation between DC/DC Converter and ADC Analog Inputs in Complex SoC
2019 Settino, Francesco; Brandtner, Thomas; Niederl, Josef; Praemassing, Frank; Koffler, Harald; Palestri, Pierpaolo; Crupi, Felice
Monte Carlo Simulation of deca-nanometer MOSFETs for Analog/Mixed-signal and RF applications
2006 Eminente, S.; Barin, N.; Palestri, Pierpaolo; Fiegna, C.; Sangiorgi, E.
System and transistor level analysis of an 8-taps FFE 10Gbps serial link transmitter with realistic channels and supply parasitics
2017 Bandiziol, Andrea; W., Grollitsch; F., Brandonisio; R., Nonis; Palestri, Pierpaolo
Design of a transmitter for high-speed serial interfaces in automotive micro-controller
2016 Bandiziol, A.; Grollitsch, W.; Brandonisio, F.; Nonis, R.; Palestri, Pierpaolo
Reduction of Up-converted Flicker Noise in differential LC-VCO designed in 32nm CMOS technology
2009 Ponton, Davide; G., Knoblinger; A., Roithmeier; M., Tiebout; M., Fulde; Palestri, Pierpaolo
An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes
2020 Okuhara, Hayate; Elnaqib, Ahmed; Rossi, Davide; Di Mauro, Alfio; Mayer, Philipp; Palestri, Pierpaolo; Benini, Luca
Efficient Quantum Mechanical Simulation of Band-to-band Tunneling
2015 Cem, Alper; Palestri, Pierpaolo; Jose L., Padilla; Antonio, Gnudi; Roberto, Grassi; Elena, Gnani; Mathieu, Luisier; Adrian M., Ionescu
Impact of Device Geometry of the Fin Electron-Hole Bilayer Tunnel FET
2016 Alper, C.; Padilla, J. L.; Palestri, Pierpaolo; Ionescu, A. M.
Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs
2017 Settino, F.; Strangio, S.; Lanuzza, M.; Crupi, F.; Palestri, P.; Esseni, D.
Two Dimensional Quantum Mechanical Simulation of Low Dimensional Tunneling Devices
2014 C., Alper; Palestri, Pierpaolo; L., Lattanzio; J. L., Padilla; A. M., Ionescu
A virtual III-V Tunnel FET technology platform for ultra-low voltage comparators and level shifters
2017 Settino, F.; Lanuzza, M.; Strangio, S.; Crupi, F.; Palestri, Pierpaolo; Esseni, David
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes | 1-gen-2018 | Dazzi, Martino; Palestri, Pierpaolo; Rossi, Davide; Bandiziol, Andrea; Loi, Igor; Bellasi, David; Benini, Luca | |
| Effect of the Grid Size on the Stability of Self-Consistent Monte-Carlo Simulations | 1-gen-2005 | N., Barin; Palestri, Pierpaolo; Esseni, David; C., Fiegna | |
| Monte-Carlo simulation of MOSFETs with Band-Offsets in the Source and Drain | 1-gen-2007 | Braccioli, M; Palestri, Pierpaolo; Poiroux, T; Vinet, M; Le Carval, G; Mouis, M; Fiegna, C; Sangiorgi, E; Deleonibus, S. | |
| Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers | 1-gen-2019 | D'Ampolo, Dylan; Bandiziol, Andrea; Menin, Davide; Grollitsch, Werner; Nonis, Roberto; Palestri, Pierpaolo | |
| Investigation on convergence and stability of self-consistent Monte Carlo device simulations | 1-gen-2002 | Clerc, R; Palestri, Pierpaolo; Abramo, Antonio | |
| Hot Carrier Degradation: From Defect Creation Modeling to Their Impact on NMOS Parameters | 1-gen-2012 | Mamy Randriamihaja, Y; Zaka, A; Huard, V; Rafik, M; Rideau, D; Roy, D; Bravaix, A; Palestri, Pierpaolo | |
| A New Model for the Backscatter Coefficient in Nanoscale MOSFETs | 1-gen-2010 | J. L. P. J., Van Der Steen; Palestri, Pierpaolo; Esseni, David; R. J. E., Hueting | |
| Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm | 1-gen-2018 | Bandiziol, Andrea; Grollitsch, Werner; Brandonisio, Francesco; Bassi, Matteo; Nonis, Roberto; Palestri, Pierpaolo | |
| Mobility in high-K metal gate UTBB-FDSOI devices: From NEGF to TCAD perspectives | 1-gen-2013 | D., Rideau; Y. M., Niquet; Nier, Oliver; A., Cros; J. P., Manceau; Palestri, Pierpaolo; Esseni, David; V. H., Nguyen; F., Triozon; J. C., Barbe; I., Duchemin; D., Garetto; L., Smith; L., Silvestri; F., Nallet; R., Clerc; O., Weber; F., Andrieu; E., Josse; C., Tavernier; H., Jaouen | |
| Package Design Methodology for Crosstalk Mitigation between DC/DC Converter and ADC Analog Inputs in Complex SoC | 1-gen-2019 | Settino, Francesco; Brandtner, Thomas; Niederl, Josef; Praemassing, Frank; Koffler, Harald; Palestri, Pierpaolo; Crupi, Felice | |
| Monte Carlo Simulation of deca-nanometer MOSFETs for Analog/Mixed-signal and RF applications | 1-gen-2006 | Eminente, S.; Barin, N.; Palestri, Pierpaolo; Fiegna, C.; Sangiorgi, E. | |
| System and transistor level analysis of an 8-taps FFE 10Gbps serial link transmitter with realistic channels and supply parasitics | 1-gen-2017 | Bandiziol, Andrea; W., Grollitsch; F., Brandonisio; R., Nonis; Palestri, Pierpaolo | |
| Design of a transmitter for high-speed serial interfaces in automotive micro-controller | 1-gen-2016 | Bandiziol, A.; Grollitsch, W.; Brandonisio, F.; Nonis, R.; Palestri, Pierpaolo | |
| Reduction of Up-converted Flicker Noise in differential LC-VCO designed in 32nm CMOS technology | 1-gen-2009 | Ponton, Davide; G., Knoblinger; A., Roithmeier; M., Tiebout; M., Fulde; Palestri, Pierpaolo | |
| An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes | 1-gen-2020 | Okuhara, Hayate; Elnaqib, Ahmed; Rossi, Davide; Di Mauro, Alfio; Mayer, Philipp; Palestri, Pierpaolo; Benini, Luca | |
| Efficient Quantum Mechanical Simulation of Band-to-band Tunneling | 1-gen-2015 | Cem, Alper; Palestri, Pierpaolo; Jose L., Padilla; Antonio, Gnudi; Roberto, Grassi; Elena, Gnani; Mathieu, Luisier; Adrian M., Ionescu | |
| Impact of Device Geometry of the Fin Electron-Hole Bilayer Tunnel FET | 1-gen-2016 | Alper, C.; Padilla, J. L.; Palestri, Pierpaolo; Ionescu, A. M. | |
| Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs | 1-gen-2017 | Settino, F.; Strangio, S.; Lanuzza, M.; Crupi, F.; Palestri, P.; Esseni, D. | |
| Two Dimensional Quantum Mechanical Simulation of Low Dimensional Tunneling Devices | 1-gen-2014 | C., Alper; Palestri, Pierpaolo; L., Lattanzio; J. L., Padilla; A. M., Ionescu | |
| A virtual III-V Tunnel FET technology platform for ultra-low voltage comparators and level shifters | 1-gen-2017 | Settino, F.; Lanuzza, M.; Strangio, S.; Crupi, F.; Palestri, Pierpaolo; Esseni, David |
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