Mechanisms Underlying the Bidirectional VT Shift After Negative-Bias Temperature Instability Stress in Carbon-Doped Fully Recessed AlGaN/GaN MIS-HEMTs

In this brief, we investigate the bidirectional threshold voltage drift (<inline-formula> <tex-math notation="LaTeX">$\Delta {V}_{T}$ </tex-math></inline-formula>) following negative-bias temperature instability (NBTI) stress in carbon-doped fully recessed AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs). Several stress conditions were applied at different: 1) gate biases (<inline-formula> <tex-math notation="LaTeX">${V}_{GS,STR}$ </tex-math></inline-formula>); 2) stress times (<inline-formula> <tex-math notation="LaTeX">${t}_{STR}$ </tex-math></inline-formula>); and 3) temperatures (<inline-formula> <tex-math notation="LaTeX">${T}$ </tex-math></inline-formula>). Both negative and positive <inline-formula> <tex-math notation="LaTeX">$\Delta {V}_{T}$ </tex-math></inline-formula> (thermally activated with different activation energies, <inline-formula> <tex-math notation="LaTeX">${E}_{A}$ </tex-math></inline-formula>) were observed depending on the magnitude of <inline-formula> <tex-math notation="LaTeX">${V}_{GS,STR}$ </tex-math></inline-formula>. In accordance with the literature, observed <inline-formula> <tex-math notation="LaTeX">$\Delta {V}_{T} < 0$ </tex-math></inline-formula> V (<inline-formula> <tex-math notation="LaTeX">${E}_{A}~\approx ~0.5$ </tex-math></inline-formula> eV) under moderate stress is attributed to the emission of electrons from oxide and interface traps. Instead, <inline-formula> <tex-math notation="LaTeX">$\Delta {V}_{T} >0$ </tex-math></inline-formula> V (<inline-formula> <tex-math notation="LaTeX">${E}_{A}~\approx ~0.9$ </tex-math></inline-formula> eV) under high stress is attributed to the increased negatively ionized acceptor trap density in the buffer associated with carbon doping.


I. INTRODUCTION
G ALLIUM nitride (GaN)-based devices have gained huge popularity in recent years due to their outstanding performance in terms of power density and operating frequency compared to Si counterparts for power switching and RF applications [1]. Conventional GaN high-electron-mobility  [2]. However, the presence of gate oxide and the associated defect-prone oxide/semiconductor interface leads to threshold voltage (V T ) instability, severely impacting device stability and operation [2]. Assessing the V T stability after negative-bias temperature stress (NBTI) is important even in normally-OFF HEMTs since V GS V T is required to avoid false turn-on when devices are pulsed at large drain voltages [3]. Moreover, if large, negative gate biases are adopted, NBTI tests are a proxy for OFFstate conditions (experienced by the device under pulse-mode operation) as similar, large values of drain-gate voltage can be achieved with both stress setups.
Different NBTI trends were observed in the literature that can be categorized as follows depending on the sign of the observed V T shifts (V T ): [7], [8]; and 3) V T of both signs, depending on device type or stress conditions [9], [10]. While V T < 0 V following NBTI is commonly attributed to the emission of electrons from traps in the gate oxide or at the interface with the semiconductor, a univocal explanation for V T > 0 V as a consequence of high negative gate bias stress is still lacking. Moreover, V T > 0 was also observed in OFF-state operating conditions, attributed to a hole generation mechanism [8], [11]. For this reason, it is worthwhile performing an in-depth analysis of V T stability after NBTI stress by exploring a wide range of stress conditions to provide a comprehensive explanation for the observed results.
In this brief, we report on an extensive characterization of V T stability in fully recessed AlGaN/GaN MIS-HEMTs under different stress conditions in terms of: 1) gate bias (V GS,STR ); 2) stress time (t STR ); and 3) temperature (T ). Depending on the V GS,STR magnitude, we observed bidirectional V T (i.e., negative and positive) and thermally activated with different activation energies, E A . In particular, we observed V T < 0 V (with E A ≈ 0.5 eV) under moderate stress 0018-9383 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
with high stress (i.e., V GS,STR = −17 V). The former behavior (V T < 0 V) can mainly be attributed to the emission of electrons from traps located in the gate oxide and/or at the interface with the semiconductor [4], [5], [9]. The latter behavior (V T > 0 V), instead, can be attributed to the increased negatively ionized acceptor traps in the buffer.

II. DEVICES DESCRIPTION
Tested devices were fully recessed AlGaN/GaN MIS-HEMTs grown by the metal-organic chemical vapor deposition on a Si(111) p-type substrate with 1-μm gate length. A schematic of the device cross section is shown in Fig. 1. The channel is composed of a low-carbon (LC)doped (∼10 16 cm −3 ) GaN layer of 0.3 μm. The GaN buffer layer instead is 4.7 μm thick and is highly C-doped (∼10 18 cm −3 ). The AlGaN barrier layer is 20 nm with 25% Al concentration. The gate dielectric (20-nm Al 2 O 3 ) is fully recessed and partially penetrates into the LC GaN (typical penetration depth is around 10 nm). This allows to effectively suppress the two-dimensional electron gas (2DEG) when no gate bias is applied, thus obtaining V T > 0 V. Ohmic contacts were formed by Ti/Al-based metallization defined by means of a liftoff process [12]. The nominal 2DEG density and mobility are 8 × 10 12 cm −2 and 1500 cm 2 /Vs, respectively. The representative transfer (I D -V GS ) and output (I D -V DS ) curves of these devices are shown in Fig. 2 (blue squares). The characterization was performed on different devices with good measurement repeatability.

III. STRESS MEASUREMENT METHODOLOGY
The NBTI stress characterization was carried out by means of a Keithley 4200 semiconductor parameter analyzer, with a thermal chuck employed for setting the device-under-test (DUT) temperature during the measurements. When applying the gate stress bias, drain and source contacts were grounded. The substrate contact was grounded by wiring the thermal chuck to the ground signal applied to the source contact. During stress, the device is periodically turned on by means of a stairway-like gate signal to monitor the V T evolution [6]. To this end, the gate is swept between -2 and 2 V with steps of 0.1 V each lasting 10 μs, whereas the drain is fixed to 0.1 V. In correspondence with each step, the drain current (I D ) and gate voltage (V GS ) are acquired, allowing the reconstruction of the I D -V GS characteristics. Since the induced stress was monitored for up to t STR = 1000 s, the gate stairway signal was applied to the DUT at logarithmically spaced time instants to ensure a uniform distribution of V T acquisitions [13]. The chosen I D -V GS sweep rate represents the best compromise between speed and accuracy since the short time required for the V T measurement minimizes the fast recovery between stress phases [6] but still provides enough samples for a correct I D -V GS acquisition. For each I D -V GS , V T was extracted with the constant-current method (I D = 0.5 mA/mm). V T is then simply calculated as (V T −V T0 ) with the reference V T0 acquired before starting the stress phase from a fresh I D -V GS curve. To determine the time constants of the V T transients to be used in the Arrhenius plots (to extract the activation energy, E A ), the curves were fitted by means of stretched exponential functions, and the relative time constants were extracted in correspondence of the peak in the dV T /dlogt STR signals.

IV. EXPERIMENTAL RESULTS
Two different stress conditions were investigated in this work, i.e., moderate (V GS,STR = -7 V) and high stress (V GS,STR = -17 V), observing V T of both signs. The measured V T evolution is shown in Figs. 3 and 4 for the moderate and high-stress conditions, respectively. Fig. 3(a) shows that, for moderate stress, V T drifts to the negative direction (i.e., becomes less than V T0 ) with a saturation V T value of about -0.8 to -1 V at t STR = 1000 s. This effect is widely reported in the literature and is attributed to the emission of electrons from traps located in the gate oxide or at the interface with the semiconductor [5], [9], which is known to be a thermally activated process [4]. In the devices tested in this work, for this process, E A ≈ 0.5 eV was estimated [see Fig. 3(b)]. The time window considered for the time constants extraction was the full stress measurement range, i.e., 1 ms-1000 s. The V T < 0 V process can also be attributed to the deionization of acceptor traps in the buffer (related to C-doping) as a consequence of the applied negative gate stress [6].
Conversely, Fig. 4(a) shows that the high-stress condition causes V T to drift in the positive direction (i.e., V T becomes larger than V T0 ). The positive drift is found to be weakly dependent on temperature for t STR in the range of 1 ms-1 s,   whereas it exhibits a clear temperature-dependent component for t STR > 1 s. E A of the latter process was found to be ≈ 0.9 eV [see Fig. 4(b)]. The time window considered for the extraction of the time constants in the Arrhenius plot, in this case, was limited to the range for which an appreciable temperature dependence was observed, i.e., 1-1000 s. Note that because no appreciable V T shift was observed for t STR > 1 s at T ≤ 50 • C, the extraction of E A from the linear fitting excluded data in this temperature range. The fast V T > 0 V can be attributed to the capture of electrons injected by the gate terminal in the oxide [7], whereas the thermally activated increase is induced by a slower process with E A ≈ 0.9 eV. To further investigate on the origin of this 0.9-eV thermally activated positive V T shift, we report the gate leakage current I G versus V GS,STR in Fig. 5. We found that for both V GS,STR = -7 and -17 V, the gate leakage current is thermally activated with E A ≈ 0.35 eV, as shown in Fig. 6. The different activation energy of I G compared to that of V T indicates that gate leakage is not the root cause for the temperature dependence of V T . E A ≈ 0.9 eV actually indicates that the observed behavior is likely caused by the dynamics of buffer acceptor traps (related to C-doping) that are energetically located at about 0.9 eV from GaN valence band edge [14]. In fact, buffer traps are known to strongly affect the behavior of AlGaN/GaN power MIS-HEMTs, as also supported by numerical simulations [15]- [20]. In this context, the thermally activated positive V T (with E A ≈ 0.9 eV) under high |V GS,STR | can be attributed to hole emission from the 0.9-eV C N acceptor traps and the consequent increase in negatively ionized C N levels. As suggested by device simulations in [19], we speculate that the emitted holes attracted at the dielectric/channel interface can recombine with electrons injected from the gate terminal. However, this phenomenon needs further investigation and will be subject of future work.

V. CONCLUSION
An in-depth experimental investigation of NBTI behavior in fully recessed AlGaN/GaN MIS-HEMTs has been presented. The results obtained by means of fast I D -V GS characterization under relatively low negative gate bias stress (i.e., V GS,STR = −7 V) revealed conventional negative V T drift associated with the thermally activated emission of electron from interface and/or oxide traps. This process was characterized by an activation energy of about 0.5 eV. Conversely, the positive V T shift observed for V GS,STR = −17 V for long stress time was ascribed to the increased negatively ionized acceptor trap density in the buffer, supported by the correlation between the extracted activation energy and the widely accepted energy level of carbon doping-related traps, both of about 0.9 eV.