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Optimization of 0.25µm GaN HEMTs through numerical simulations

0.25µm GaN HEMTs performance dependence from epitaxial and geometrical parameters has been investigated by means of numerical simulations. A single-heterojunction GaN HEMT structure with an iron doped buffer layer also including a mushroom-gate layout forming a gate-connected field-plate over the ...

High electron mobility transistor HEMT device

This disclosed embodiment relates to a high electron mobility transistor HEMT device. This HEMT device includes: the semiconductor main part is including heterostructure, dielectric layer in the semiconductor main part, gate electrode, the drain electrode is towards gate electrode's first sid...

Normal shutoff type HEMT transistor

The utility model relates to a normal shutoff type HEMT transistor. A normal shutoff type HEMT transistor includes: semiconductor heterojunction (4, 6, 200), it includes one first layer (4) and one the second floor (6) at least, the second floor is arranged on the top of&...

Enhancement-/depletion-PHEMT device and manufacturing method thereof

The present invention relates, in general, to enhancement/ depletion Pseudomorphic High Electron Mobility Transistors (PHEMTs) and, in particular, to an enhancement/depletion PHEMT device and a method for manufacturing enhancement/depletion PHEMT devices that finds advantageous, but not exclusiv...

Fabrication of single or multiple gate field plates

A method of manufacturing a single or multiple gate field plates, which utilizes the following successive steps of: depositing a dielectric material / grown on the surface of the field effect transistor, etching the dielectric material and a metal vapor deposition. Since the d...