A sub-harmonic architecture for wireless signal processing at Ka band is proposed resulting in IC power saving because the LO circuits operate at half frequency and no IF stage is necessary. A 65nm CMOS prototype, including High Frequency front-end, base-band amplifier and multi-phase VCO and dividers, shows: 31.5dB gain, 6.5dB NF, -17dBm IIP3, -90dBm LO re-irradiation at 24GHz, while consuming 92mW.
A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS / Mazzanti, Andrea; M., Sosio; M., Repossi; F., Svelto. - STAMPA. - 51:(2008), pp. 216-217. (Intervento presentato al convegno IEEE International Solid State Circuit Conference (ISSCC), Digest of Techncal Papers tenutosi a San Francisco nel Febbraio 2008).
A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS
MAZZANTI, Andrea;
2008
Abstract
A sub-harmonic architecture for wireless signal processing at Ka band is proposed resulting in IC power saving because the LO circuits operate at half frequency and no IF stage is necessary. A 65nm CMOS prototype, including High Frequency front-end, base-band amplifier and multi-phase VCO and dividers, shows: 31.5dB gain, 6.5dB NF, -17dBm IIP3, -90dBm LO re-irradiation at 24GHz, while consuming 92mW.
Pubblicazioni consigliate
I metadati presenti in IRIS UNIMORE sono rilasciati con licenza Creative Commons CC0 1.0 Universal, mentre i file delle pubblicazioni sono rilasciati con licenza Attribuzione 4.0 Internazionale (CC BY 4.0), salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris
