In this paper, deep levels are characterized in 6H-SiC, buried gate, n-channel JFETs by means of capacitance-mode (C-) and current-mode (I-) Deep Level Transient Spectroscopy (DLTS) and transconductance frequency dispersion measurements. Moreover, the drain-current transients following a gate-to-source voltage step are analyzed both experimentally and through two-dimensional device simulations allowing the dierent deep levels to be localized both energetically and spatially.
Trap-related effects in 6H-SiC buried-gate JFETs / G., Meneghesso; Chini, Alessandro; E., Zanoni; Verzellesi, Giovanni; Tediosi, Erika; Canali, Claudio; A., Cavallini; A., Castaldini. - STAMPA. - (2001), pp. 169-170. (Intervento presentato al convegno Workshop On Compound Semiconductor Devices and Integrated Circuits held in Europe (WOCSDICE) tenutosi a Quartu S. Elena (Cagliari, Italy) nel May 2001).
Trap-related effects in 6H-SiC buried-gate JFETs
CHINI, Alessandro;VERZELLESI, Giovanni;TEDIOSI, Erika;CANALI, Claudio;
2001
Abstract
In this paper, deep levels are characterized in 6H-SiC, buried gate, n-channel JFETs by means of capacitance-mode (C-) and current-mode (I-) Deep Level Transient Spectroscopy (DLTS) and transconductance frequency dispersion measurements. Moreover, the drain-current transients following a gate-to-source voltage step are analyzed both experimentally and through two-dimensional device simulations allowing the dierent deep levels to be localized both energetically and spatially.Pubblicazioni consigliate
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