This paper presents a new compact model of Floating Gate Non-Volatile Memory Cells using SPICE circuit elements. It features many advantages compared to previous models: it is simple and easy to implement, scalable, and its computational time is not critical, thus making it very attractive to industry. It is based on a new procedure that improves the floating gate voltage estimate. The parameter extraction procedure is the same of a MOS transistor.
A New Compact Model of Floating Gate Non-Volatile Memory Cells / Larcher, Luca; Pavan, Paolo; F., Gattel; L., Albani; A., Marmiroli. - STAMPA. - (2001), pp. 56-59. (Intervento presentato al convegno Technical Proceedings of Fourth International Conference on Modeling and Simulation of Microsystems tenutosi a Hilton Head Island (SC, USA) nel 19/21 March 2001).
A New Compact Model of Floating Gate Non-Volatile Memory Cells
LARCHER, Luca;PAVAN, Paolo;
2001
Abstract
This paper presents a new compact model of Floating Gate Non-Volatile Memory Cells using SPICE circuit elements. It features many advantages compared to previous models: it is simple and easy to implement, scalable, and its computational time is not critical, thus making it very attractive to industry. It is based on a new procedure that improves the floating gate voltage estimate. The parameter extraction procedure is the same of a MOS transistor.
Pubblicazioni consigliate
I metadati presenti in IRIS UNIMORE sono rilasciati con licenza Creative Commons CC0 1.0 Universal, mentre i file delle pubblicazioni sono rilasciati con licenza Attribuzione 4.0 Internazionale (CC BY 4.0), salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris
