Despite large efforts in research of HfO 2 -based ferroelectric (FE) random access memories (FRAM), mechanisms underlying the device behavior of and its reliability (premature degradation) are poorly understood. To tackle this issue, we used a multiscale modeling framework that allows investigating the interplay between the FE switching, defects and polycrystalline nature of the HfO 2 material. This multiscale model allows connecting the electrical performances of FE devices (e.g. switching) to the atomic material properties, including defects and morphology (e.g. material phase). We used this simulation platform to both study wake-up process and the device-to-device variability in different memory architectures, i.e. capacitor-based FRAM and ferroelectric tunnel junction (FTJ) and the ferroelectric FET (FeFET) subjected to high field program/erase stress.
Multiscale Modeling of Ferroelectric Memories: Insights into Performances and Reliability / Pesiu, M.; Di Lecce, V.; Pramanik, D.; Larcher, L.. - 2018-:(2018), pp. 111-114. (Intervento presentato al convegno 2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018 tenutosi a AT and T Hotel and Conference Center, usa nel 2018) [10.1109/SISPAD.2018.8551722].
Multiscale Modeling of Ferroelectric Memories: Insights into Performances and Reliability
Di Lecce V.;Larcher L.
2018
Abstract
Despite large efforts in research of HfO 2 -based ferroelectric (FE) random access memories (FRAM), mechanisms underlying the device behavior of and its reliability (premature degradation) are poorly understood. To tackle this issue, we used a multiscale modeling framework that allows investigating the interplay between the FE switching, defects and polycrystalline nature of the HfO 2 material. This multiscale model allows connecting the electrical performances of FE devices (e.g. switching) to the atomic material properties, including defects and morphology (e.g. material phase). We used this simulation platform to both study wake-up process and the device-to-device variability in different memory architectures, i.e. capacitor-based FRAM and ferroelectric tunnel junction (FTJ) and the ferroelectric FET (FeFET) subjected to high field program/erase stress.
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