Architectural heterogeneity is a promising solution to overcome the utilization wall and provide Moore's Law-like performance scaling in future SoCs. However, heterogeneous architectures increase the size and complexity of the design space, and significant enhancements are required to tools and methodologies to explore this design space effectively. In this work, we describe an extension to the STMicroelectronics P2012 platform and simulation flow to support tightly-coupled shared memory HW processing elements (HWPE), we propose a methodology for the semi-automatic instantiation of HWPEs from a C program, and we explore several architectural variants on a set of computer vision benchmarks.
He-P2012: Architectural heterogeneity exploration on a scalable many-core platform / Conti, Francesco; Pilkington, Chuck; Marongiu, Andrea; Benini, Luca. - STAMPA. - (2014), pp. 231-232. (Intervento presentato al convegno 24th Great Lakes Symposium on VLSI, GLSVLSI 2014 tenutosi a Houston, TX, usa nel 2014) [10.1145/2591513.2591553].
He-P2012: Architectural heterogeneity exploration on a scalable many-core platform
Marongiu Andrea;
2014
Abstract
Architectural heterogeneity is a promising solution to overcome the utilization wall and provide Moore's Law-like performance scaling in future SoCs. However, heterogeneous architectures increase the size and complexity of the design space, and significant enhancements are required to tools and methodologies to explore this design space effectively. In this work, we describe an extension to the STMicroelectronics P2012 platform and simulation flow to support tightly-coupled shared memory HW processing elements (HWPE), we propose a methodology for the semi-automatic instantiation of HWPEs from a C program, and we explore several architectural variants on a set of computer vision benchmarks.
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