Leakage power has become a major concern in nanometer technologies (65nm and beyond), and new strategies are being proposed to overcome the limitations of traditional dynamic voltage and frequency scaling (DVFS) and shutdown (SD) approaches in dealing with leakage power and with its strong dependency on temperature and process variations. Even though many researchers have proposed effective point-solutions to these issues, a detailed analysis of their impact on a commercial large-scale multimedia SoC platform is still missing. This paper presents an explorative and comparative analysis of DVFS and SD power management options on a multi-million-gate SoC in 65nm technology, and provides methodology directions and design insights

Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology / Marongiu, Andrea; Acquaviva, Andrea; Benini, Luca; Bartolini, Andrea. - STAMPA. - (2008), pp. 259-266. (Intervento presentato al convegno 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008 tenutosi a Parma, Italy nel 3-5 Sept. 2008) [10.1109/DSD.2008.100].

Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology

MARONGIU, ANDREA;
2008

Abstract

Leakage power has become a major concern in nanometer technologies (65nm and beyond), and new strategies are being proposed to overcome the limitations of traditional dynamic voltage and frequency scaling (DVFS) and shutdown (SD) approaches in dealing with leakage power and with its strong dependency on temperature and process variations. Even though many researchers have proposed effective point-solutions to these issues, a detailed analysis of their impact on a commercial large-scale multimedia SoC platform is still missing. This paper presents an explorative and comparative analysis of DVFS and SD power management options on a multi-million-gate SoC in 65nm technology, and provides methodology directions and design insights
2008
11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008
Parma, Italy
3-5 Sept. 2008
259
266
Marongiu, Andrea; Acquaviva, Andrea; Benini, Luca; Bartolini, Andrea
Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology / Marongiu, Andrea; Acquaviva, Andrea; Benini, Luca; Bartolini, Andrea. - STAMPA. - (2008), pp. 259-266. (Intervento presentato al convegno 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008 tenutosi a Parma, Italy nel 3-5 Sept. 2008) [10.1109/DSD.2008.100].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1171884
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