An improved procedure to extract the limiting carrier velocity in ultra scaled CMOS devices

The validity of a previously published extraction technique for the limiting carrier velocity responsible for current saturation in nano-MOSFETs is carefully re-examined by means of accurate Multi Subband Monte Carlo transport simulations. By comparing the extracted limiting velocity to the calculated injection velocity, we identify the main sources of error of the extraction method. Then, we propose a new extraction procedure and extensively validate it. Our simulations and experimental results reconcile the values and trends of the extracted limiting velocity with the expectations stemming from quasi ballistic transport theory.