The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications . Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA). Unfortunately in all cases a relatively large average SS and a poor on-current have been observed. In conclusion with this work we have shown that although commonly fabricated TFETs feature source/channel interfaces normal to the transport direction, in a well-designed TFET the tunneling junction should have the same orientation of the component of the electric field modulated by the gate: only in this case the gate can effectively modulate the tunneling barrier, resulting in a steeper average SS and higher ION.

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier / DE MICHIELIS, Luca; Lattanzio, L; Palestri, Pierpaolo; Selmi, Luca; Ionescu, A. M.. - (2011), pp. 111-112. (Intervento presentato al convegno 69th Annual Device Research Conference (DRC), 2011 tenutosi a Santa Barbara, CA, 20-22 June 2011 nel June 2011) [10.1109/DRC.2011.5994440].

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

PALESTRI, Pierpaolo;SELMI, Luca;
2011

Abstract

The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications . Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA). Unfortunately in all cases a relatively large average SS and a poor on-current have been observed. In conclusion with this work we have shown that although commonly fabricated TFETs feature source/channel interfaces normal to the transport direction, in a well-designed TFET the tunneling junction should have the same orientation of the component of the electric field modulated by the gate: only in this case the gate can effectively modulate the tunneling barrier, resulting in a steeper average SS and higher ION.
2011
69th Annual Device Research Conference (DRC), 2011
Santa Barbara, CA, 20-22 June 2011
June 2011
111
112
DE MICHIELIS, Luca; Lattanzio, L; Palestri, Pierpaolo; Selmi, Luca; Ionescu, A. M.
Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier / DE MICHIELIS, Luca; Lattanzio, L; Palestri, Pierpaolo; Selmi, Luca; Ionescu, A. M.. - (2011), pp. 111-112. (Intervento presentato al convegno 69th Annual Device Research Conference (DRC), 2011 tenutosi a Santa Barbara, CA, 20-22 June 2011 nel June 2011) [10.1109/DRC.2011.5994440].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1162846
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