Vai a: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Mostrati risultati da 1 a 17 di 17
Titolo Data di pubblicazione Autore(i) File
A review of failure modes and mechanisms of GaN-based HEMTs 1-gen-2007 E., Zanoni; G., Meneghesso; Verzellesi, Giovanni; F., Danesin; M., Meneghini; F., Rampazzo; A., Tazzoli; F., Zanon
Application and benefits of target programming algorithms for ferroelectric HfO2transistors 1-gen-2020 Zhou, H.; Ocker, J.; Padovani, A.; Pesic, M.; Trentzsch, M.; Dunkel, S.; Mulaosmanovic, H.; Slesazeck, S.; Larcher, L.; Beyer, S.; Muller, S.; Mikolajick, T.
Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric 1-gen-2008 G., Bersuker; D., Heh; C., Young; H., Park; P., Khanal; Larcher, Luca; Padovani, Andrea; P., Lenahan; J., Ryan; B. H., Lee; H., Tseng; R., Jammy
CMOS and Interconnect Reliability - Flash Reliability/Hot Carrier Effects 1-gen-2003 Pavan, P.; Owens, A.
Coexistence of volatile and non-volatile resistive switching in 2D h-BN based electronic synapses 1-gen-2018 Shi, Y.; Pan, C.; Chen, V.; Raghavan, N.; Pey, K. L.; Puglisi, F. M.; Pop, E.; Wong, H. -S. P.; Lanza, M.
Deconvoluting charge trapping and nucleation interplay in FeFETs: Kinetics and Reliability 1-gen-2019 Pesic, M.; Padovani, A.; Slcsazeck, S.; Mikolajick, T.; Larcher, L.
Design and Optimization of β-Ga 2 O 3 on (h-BN layered) Sapphire for High Efficiency Power Transistors: A Device-Circuit-Package Perspective 1-gen-2018 Mahajan, B. K.; Chen, Y. -P.; Ahn, W.; Zagni, N.; Alam, M. A.
An Experimental Study of Low Field Electron Mobility in Double-Gate, Ultra-Thin SOI MOSFETs 1-gen-2001 Esseni, David; M., Mastrapasqua; C., Fiegna; G. K., Celler; Selmi, Luca; Sangiorgi, Enrico
Investigating the Statistical-Physical Nature of MgO Dielectric Breakdown in STT-MRAM at Different Operating Conditions 1-gen-2019 Lim, J. H.; Raghavan, N.; Padovani, A.; Kwon, J. H.; Yamane, K.; Yang, H.; Naik, V. B.; Larcher, L.; Lee, K. H.; Pey, K. L.
Investigation of the role of H-related defects in Al2O3 blocking layer on charge-trap memory retention by atomistic simulations and device physical modelling 1-gen-2010 Molas, G.; Masoero, L.; Blaise, P.; Padovani, A.; Colonna, J. P.; Vianello, E.; Bocquet, M.; Nowak, E.; Gasulla, M.; Cueto, O.; Grampeix, H.; Martin, F.; Kies, R.; Brianceau, P.; Gely, M.; Papon, A. M.; Lafond, D.; Barnes, J. P.; Licitra, C.; Ghibaudo, G.; Larcher, L.; Deleonibus, S.; De Salvo, B.
Multiscale modeling of neuromorphic computing: From materials to device operations 1-gen-2018 Larcher, L.; Padovani, A.; Di Lecce, V.
New model of tunnelling current and SILC in ultra-thin oxides 1-gen-1998 Larcher, L.; Paccagnella, A.; Scarpa, A.; Ghidini, G.
A novel degradation mechanism of AlGaN/GaN/Silicon heterostructures related to the generation of interface traps 1-gen-2012 Meneghini, M.; Bertin, M.; Dal Santo, G.; Stocco, A.; Chini, Alessandro; Marcon, D.; Malinowski, P. E.; Mura, G.; Musu, E.; Vanzi, M.; Meneghesso, G.; Zanoni, E.
Quantitative assessment of mobility degradation by remote coulomb scattering in ultra-thin oxide MOSFETs: Measurements and simulations 1-gen-2003 Lucci, L.; Esseni, D.; Loo, J.; Ponomarev, Y.; Selmi, L.; Abramo, A.; Sangiorgi, E.
Quantum electronics and compound semiconductors - HEMTs: Physics and new technologies 1-gen-2004 Suemitsu, T.; Verzellesi, G.
A scaled replacement metal gate InGaAs-on-Insulator n-FinFET on Si with record performance 1-gen-2017 Hahn, H.; Deshpande, V.; Caruso, E.; Sant, S.; O'Connor, E.; Baumgartner, Y.; Sousa, M.; Caimi, D.; Olziersky, A.; Palestri, P.; Selmi, L.; Schenk, A.; Czornomaz, L.
A simulation study of strain induced performance enhancements in InAs nanowire Tunnel-FETs 1-gen-2011 Conzatti, Francesco; M. G., Pala; Esseni, David; E., Bano; Selmi, Luca
Mostrati risultati da 1 a 17 di 17
Legenda icone

  •  file ad accesso aperto
  •  file disponibili sulla rete interna
  •  file disponibili agli utenti autorizzati
  •  file disponibili solo agli amministratori
  •  file sotto embargo
  •  nessun file disponibile