A memory window expression to evaluate the endurance of ferroelectric FETs

The recent discovery of ferroelectricity in HfO2 has revived the interest into non-volatile memories based on ferroelectric transistors (FeFETs). Among their advantages stand out the low power consumption and the compatibility with existing CMOS process. On the other hand, issues related mainly to endurance still represent a challenge to the development of the technology. In this letter, we propose to exploit an analytical expression for the Memory Window (MW ) as a simple yet effective characterization tool to evaluate endurance in FeFETs. MW is defined as the difference between threshold voltages occurring due to polarization switching. The analytical formulation of MW allows one to quickly estimate the generated trap concentration as a function of number of writing cycles (or time) without recurring to numerical simulations. With the aid of the analytical model, we find that for a specific set of program/erase pulse amplitude and duration, endurance has weak dependence on writing conditions. The characterization technique based on MW would allow the systematic comparison of the performance and endurance of next-generation FeFETs.

The recent discovery of ferroelectricity in HfO 2 has revived the interest into non-volatile memories based on ferroelectric transistors (FeFETs). Among their advantages stand out the low power consumption and the compatibility with existing CMOS process. On the other hand, issues related mainly to endurance still represent a challenge to the development of the technology. In this letter, we propose to exploit an analytical expression for the Memory Window (MW ) as a simple yet effective characterization tool to evaluate endurance in FeFETs. MW is defined as the difference between threshold voltages occurring due to polarization switching. The analytical formulation of MW allows one to quickly estimate the generated trap concentration as a function of number of writing cycles (or time) without recurring to numerical simulations. With the aid of the analytical model, we find that for a specific set of program/erase pulse amplitude and duration, endurance has weak dependence on writing conditions. The characterization technique based on MW would allow the systematic comparison of the performance and endurance of next-generation FeFETs.
The first demonstration in the early 1960s of a thin-film ferroelectric transistor (FeFET) by Moll and Tarui 1 started the quest for realizing low-power and efficient Non-Volatile Memories (NVMs) based on this technology. After more than fifty years, the discovery of ferroelectricity in binary oxides such as HfO 2 and ZrO 2 revived the interest of the community in the FeFET technology [2][3][4] . FeFETs in fact, offer a wide range of improvements in terms of nonvolatility, scaling potential, read-write speed, and power dissipation with respect to DRAM, SRAM and Flash memory 2 . However, issues at device level limiting retention, and -mostly -endurance still need to be solved. In fact, while HfO 2 -based FeFETs have reduced trapping and lower depolarization over coercive field ratio -leading to improved retention time with respect to older device generations based on PZT or SBT ferroelectrics 5 -endurance is still a major issue. Indeed, recent reports showed that endurance typical range is ∼ 10 4 − 10 6 writing cycles 6,7 ; this is far from meeting the International Roadmap for Devices and Systems (IRDS) requirements of 10 12 cycles 8 . Nonetheless, the successful demonstration of a ultra-scaled CMOS-compatible FeFET would advance a broad range of applications, such as: i) Logic-In-Memory (LiM) circuits 9 ; ii) artificial neural networks 10,11 ; and iii) Ternary Content Addressable Memories (TCAMs) 9,11 .
Thus, deployment of characterization tools that quantify and identify the limiting factors to endurance would facilitate the development of next-generation FeFETs 12 . In this letter, we propose to evaluate the endurance of FeFETs by using a simple characterization tool based on an analytical expression of the Memory Window (MW ). The MW expression allows quantifying the impact of oxide and interface traps generated over time. In addition, from the MW expression it is possible to estimate the generated trap concentration during endurance tests without the need for numerical TCAD simulations. We find also that under specific assumptions regarding the program/erase pulse amplitude and duration endurance weakly depends on writing conditions. The MW is expressed as the difference between the onand off-threshold voltage (V th,on , and V th,o f f ) that correspond to the right and left path of the FeFET I D − V GS characteristics 3 , respectively. These path differ because of polarization switching and represent the logic binary states "0" and "1" of the memory. The expressions for V th,on , and V th,o f f used in this work are a generalization of the ones derived by Chen et al. 13 for a Metal-Ferroelectric-Insulator-Semiconductor (MFIS) stack. The MW is then simply written as V th,on − V th,o f f . The derivation is based on the electrostatic behavior of the FeFET described by the MOSFET surface potential equation (SPE) 13,14 : where V GS is the applied gate-source bias, V FB is the flatband voltage, V ins is the insulator voltage (including both ferroelectric and oxide interface layer), and ψ s is the surface potential. V ins includes the contribution from the ferroelectric and oxide interlayer and is expressed as follows: where C ox = ε ox /t ox is the oxide capacitance (SiO 2 in this work) and C FE is the ferroelectric capacitance. The latter can be written in a compact form by using the Landau-Devonshire (LD) theory 13,15 : where Q s is the semiconductor charge, α, β are the Landau parameters for the ferroelectric layer, ε FE is the parameter accounting for the dielectric response of the ferroelectric layer 16,17 , and t FE is the ferroelectric thickness. The two terms This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset. PLEASE CITE THIS ARTICLE AS DOI: 10.1063/5.0021081 in Eq. (3) reflect the contributions to the displacement of the electric field (D) obtained from the spontaneous polarization and the applied electric field 16 , i.e., D = ε F E E + P. Incidentally, we mention that the LD formulation of C FE is commonly employed to describe the operation of Negative Capacitance transistors (NCFETs) for logic 15 and other applications (such as bio-sensing 18 ). However, it can be used also to model the operation of hysteretic FeFETs 13 . Thus, the approach based on the LD theory followed in this work can serve as a bridge between the NC-and Fe-FETs communities thanks to their common theoretical framework. The closed-form expressions for V th,on , V th,o f f and MW read as (see the Supplementary Material for the derivation): ε s is the semiconductor dielectric constant, n i is the intrinsic carrier density, and N a is the substrate doping density (for a p-type substrate in a NMOS device). V sw is the V ins at which switching from off-to on-occurs (Q sw is the corresponding charge). V sw and Q sw are calculated following the procedure described in the Supplementary Material. Since V sw ∝ t FE , and MW ∼ V sw ∝ t FE , Eq. (6) correctly anticipates the theoretical (and experimentally observed) linear thickness-dependence of the MW 4,14,19 . While the traditional Preisach model could also be used to describe the hysteretic polarization behavior 14 , it does not allow to de-couple V FE (ferroelectric voltage) from P 14,20 and thus requires a selfconsistent, numerical analysis to obtain the results. Instead, relying on the LD theory allows to derive simple, closed-form expressions as (4)-(6) (and subsequent ones). More details regarding the derivation and approximations introduced as well as the applicability limits of the analytical model are given in the Supplementary Material.
Endurance is defined as the time taken (or total number of cycles) during repeated program/erase operations before the "0" and "1" states become indistinguishable. The main limiting factor to FeFETs endurance is the trap generation in the oxide interlayer between the ferroelectric and the semiconductor body 22 . This effect is the subject of investigation in this work. Other limitations to endurance of these devices are related to ferroelectric aging that might lead to additional V th 's shifts, premature breakdown due to formation of percolation paths 23,24 and remnant polarization degradation 22 . A more detailed discussion on these effects is given in the Supplementary Material. We do not explicitly take into account the fast MW decay (due to depolarization fields and trapping/detrapping) because it is expected to mainly influence retention 5,22 .
During stress tests to probe endurance, the high electric field in the gate stack accelerates trap generation. The electric field mainly concentrates on the oxide interlayer rather than in the ferroelectric because of its lower dielectric constant 20 . Thus, generation is assumed to only occur at the oxide/semiconductor interface and in the oxide itself. The effect of generated defects is modeled by adding to the righthand side of Eq. (1) these additional terms 25 : where ∆N ot is the generated trap concentration in the oxide interface layer (cm −2 ), ∆D it is the generated interface trap density of states (cm −2 eV −1 ), and φ b is the body potential We assume that the charge neutrality level for the interface traps is located at Si mid-gap 25 . Stress is induced by positive and negative pulses applied on the gate to erase and program the FeFET, respectively. Hence, V th,on tends to decrease and V th,o f f to increase 21 . The concentration of generated defects during writing of the memory is in general different depending on the sign of the writing pulse, therefore the shifts in V th,on and V th,o f f are not symmetric. This is reflected in the different symbols used to indicate the generated defects during program and erase cycles, namely, ∆N ot,P⁄E and ∆D it,P⁄E for oxide and interface traps, respectively.
The degraded V th,on , V tho f f , and MW expressions are modified by taking into account the additional potential drops due to defects expressed in Eq. (7) (see the Supplementary Material for the derivation). The V th 's and MW variation is expressed as follows: To assess the accuracy of the above expressions, we compared the analytical results with experimental data of endurance tests from Ref. 21 26 . That is, N ot and D it were extracted by separating the threshold voltage shifts due to oxide (∆V mg ) and interface traps (∆V it ) separately. The former is obtained from the midgap voltage, V mg , that correlates with N ot -induced V th drifts as at V G = V mg ⇒ ψ s = φ b and ∆V it = 0, see Eq. (7); the latter is obtained by letting ∆V it = ∆V th − ∆V ot 21,26 . To summarize, Eq. (8a)-Eq. (8c) directly connect the FeFET parameters to the stress-dependent oxide and interface trap generation. As such, Eq. (8c) represents the proposed MW -based characterization tool for extracting oxide and interface defects. This could serve either as an alternative to traditional techniques, or as a stand-alone method to characterize defect densities under a variety of stress conditions. For instance, notice that when only N ot generation affects MW degradation then it is possible to estimate the net generated traps from the simplified ∆MW ′ This expression allows to simply and directly correlate MW measurements with generated traps. In the following we show that the endurance extrapolated from the equations derived previously is weakly influenced by the writing conditions (in terms of |V P/E | and t P/E ). With the N ot and D it data extracted from Fig. 2, it is possible to extrapolate the generated trap concentration for an arbitrary number of writing cycles. For simplicity and clarity of presentation, we assume that the MW degradation is induced by oxide traps only (as supported by the experimental data from 21) and neglect the generation of interface traps. The generated oxide trap density, N ot is shown in Fig. 3(a), (b) for both program and erase operation that set V th,on and V th,o f f , respectively. By fitting the experimental data in Fig. 3 it is found that generated oxide trap concentration follows a power law with respect to writing time (with t cycle = 200ns): The values of N 0 and β s coefficients are collected in Table I for different writing conditions. Exponent β s is in the range This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset. The extrapolated MW degradation obtained by using the predicted ∆N ot from the generation model is shown in Fig. 4(a), (b) for different V P/E and t P/E values, respectively. Note that MW values are normalized to the respective initial value for a fair comparison with different writing conditions. The FeFET is considered to fail to retain its memory operation after reaching the arbitrary threshold set as the 20% of the initial MW , see Fig. 4. That is, endurance is defined as the number of cycles at which MW reaches 20% of its initial value. Interestingly, notice from Fig. 4(a) that |V P/E | increment does not degrade endurance significantly (at least for the range of values as in Ref. 21). This is because higher |V P/E | leads to higher initial MW 4 but also higher ∆N ot , see Fig. 3. Similarly, Fig. 4(b) shows that increasing the pulse duration negligibly influences endurance. Note that in this case it was assumed that t P/E increase leads to the same increase in MW and initial N ot to that caused by V P/E . This was done for the specific purpose of illustrating that if both MW and initial N ot increase with program conditions, then the combined effect leads to negligible variation in endurance. However, if the assumption regarding MW and N ot increase with V P/E (or t P/E ) is not satisfied, then the endurance limit will be affected by the writing conditions.

PLEASE CITE THIS ARTICLE AS
The model can also predict the endurance improvement obtained if the generated trap are decreased, either by improving the SiO 2 /Si interface quality or by reducing the field in the oxide layer. For instance, if N 0 is decreased by one order of magnitude (and assuming every other parameter constant) then endurance can be extended to 10 6 cycles.
Endurance improvements where observed also in experiments employing either: i) unipolar stress pulses instead of conventional, bipolar ones 22 ; or ii) large-area samples with improved interface quality and low gate leakage 28 . These results can be predicted by the developed analytical model, provided that adequate degradation model (i.e., by choosing proper N 0 and β s in Table I) is employed.
In this letter, we evaluated the endurance of FeFETs by using an analytical expression of the Memory Window, MW , for the conventional MFIS structure. The MW expression takes into account the contribution from generated interface TABLE I. Coefficients of the power law in Eq. (10). and oxide traps and was validated against experimental data. We find that: (i) MW can be used to extract oxide and interface traps being generated during endurance tests, see Eq. (9); (ii) the generation trend follows a power-law with time exponent ∼ 0.3 − 0.5, see Eq. (10); and (iii) under specific assumptions, the endurance limit is essentially independent of writing conditions, see Fig. 4. The considerations drawn from the simple analytical formulation can be helpful to develop next-generation FeFET with improved endurance.

SUPPLEMENTARY MATERIAL
See supplementary material for: (i) the detailed derivation of the analytical expressions; (ii) the design constraints to ensure hysteretic operation; (iii) the applicability limits of the analytical approach; and (iv) the limiting factors to endurance related to ferroelectric aging.

ACKNOWLEDGMENT
The authors thank Thomas Mikolajick (NaMLab, TU Dresden), Francesco Maria Puglisi (University of Modena and Reggio Emilia), and Kamal Karda (Purdue University) for the valuable discussions.

DATA AVAILABILITY
The data that support the findings of this study are available from the corresponding author upon reasonable request.  This is the author's peer reviewed, accepted manuscript. However, the online version of record will be different from this version once it has been copyedited and typeset. PLEASE CITE THIS ARTICLE AS DOI: 10.1063/5.0021081