Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-Of-The-Roadmap III-V MOSFETs

 Abstract— Thanks to their superior transport properties, Indium Gallium Arsenide (InGaAs) Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) constitute an alternative to conventional Silicon MOSFETs for digital applications at ultra-scaled nodes. The successful integration of this technology is challenged mainly by the high defect density in the gate oxide and at the interface with the semiconductor channel, which degrades the electrostatics and could limit the potential benefits over Si. In this work, we i) establish a systematic modeling approach to evaluate the performance degradation due to interface traps in terms of electrostatics and transport of InGaAs Dual-Gate Ultra-Thin Body (DG-UTB) FETs, and ii) investigate the effects of random interface-trap concentration as another roadblock to the scaling of the technology, due to statistical variability of the threshold voltage. Variability is assessed with a Technology CAD (TCAD) simulator calibrated against Multi-Subband Monte Carlo (MSMC) simulations. The modeling approach overcomes the TCAD limitations when dealing with ultra-thin channels (i.e., below 5 nm) without altering crucial geometrical parameters that would compromise the dependability of the variability analysis. Our results indicate that interface-trap fluctuation becomes comparable with the other variability sources dominating the total variability when shrinking the device dimensions, thus contrasting the trend of reduced variability with scaling. This in turn implies that interface and border traps may strongly limit the benefits of InGaAs over Silicon if not effectively reduced by gate process optimization.


I. INTRODUCTION
OW effective-mass semiconductors such as In0.53Ga0.47Asare widely explored as possible replacement of Silicon for end-of-the-roadmap MOSFETs thanks to their high electron mobility and injection velocity [1], [2].Besides the wellknown limit of In0.53Ga0.47Asrelated to the low Density of States (DOS) in thin films operating in the quantum limit reducing the maximum achievable electron density [3], the most detrimental issue related to this technology is the high defect density in the gate oxide and at the interface with the channel [4]- [6].In fact, defects reduce the electron mobility and degrade the electrostatic integrity of the devices, thus partially compensating the benefits of InGaAs over Si MOSFETs.In addition, another major roadblock to the successful scaling of InGaAs technology is related to the statistical (or local) variability [7] that causes identically drawn devices to have different performance [8].
In this work, we establish a systematic modeling approach that allows assessing the performance degradation due to interface traps (in terms of electrostatic and transport behavior) of DG-UTB devices.In addition, we evaluate the effects of random interface-trap concentration on the variability of the threshold voltage (VT).The variability analysis is performed with a TCAD simulator via the statistical Impedance Field Method (IFM) [9], [10] that allows obtaining accurate results with limited computational time compared to the more sophisticated approaches of MSMC or atomistic simulators [11].The design of the DG-UTB devices is developed by following the ITRS indications for Ge/III-V semiconductors [12], carefully adjusted to preserve electrostatic integrity and to limit leakage due to Source-to-Drain Tunneling (SDT) [13].The device characteristics and associated variability are evaluated with the TCAD simulator with a quantum-corrected Drift Diffusion model (QDD), calibrated against MSMC simulations.The calibration was successfully achieved by implementing a systematic calibration procedure that overcomes the limitations of TCAD related to the electron-wave-function distribution when The variability analysis was carried out with the addition of the Interface-Trap Fluctuation (ITF) source to other variability sources, namely: i) Random-Dopant Fluctuation (RDF) [14]; ii) gate metal Work-Function Fluctuation (WFF) [15]; iii) InGaAs Band-Gap Fluctuation (BGF) [16]; and iv) Body-and Gate-Line-Edge Roughness (BLER, GLER) [8].
The variability analysis here presented complements the research previously carried out by the authors [9], [16], with the inclusion of ITF.Moreover, it allows determining the impact of randomized interface-trap concentration on the total variability providing insights into the limitations of InGaAstechnology scaling.The variability due to random interfacetrap density (DIT), trap number, and location was evaluated for Si Multi-Gate (MG) MOSFETs finding that its impact increases due to the generation of defects as a consequence of aging [14], [17], [18].As InGaAs MOSFETs exhibit higher native DIT (i.e., even before degradation due to aging) compared to Si [19], here we focus on the variability to assess due to native interface traps.The employed DIT energy distribution was derived from a distribution matching experimental data that also reproduced mobility degradation and transfer-characteristic hysteresis in InGaAs devices [5], [13], [19], [20].The systematic modeling approach developed in this work provides a consistent agreement between QDD and MSMC not only in terms of the transfer-characteristics (ID-VGS curve) but also in terms of inversion and trappedcharge density in the channel, as well as the mobility.Thus, electrostatic and transport properties were correctly simulated without altering sensitive parameters such as the body/channel thickness as done in previous works [21], which is critical to provide meaningful variability predictions.The methodology developed in this work could potentially be extended to other III-V devices when considering the effects of interface traps on extremely scaled structures for which experimental data is lacking and calibration of TCAD on more sophisticated simulators is required.
The rest of the paper is organized as follows.In Sections II and III, we describe the methodology used to model the interface-trap effects within the MSMC simulations and to calibrate the QDD over the MSMC simulations, respectively.In Section IV, the modeling of the variability sources and the methodology to calculate the performance variations is discussed.Then, the variability results obtained for VT are shown, along with a discussion on the effects of scaling and a comparison between InGaAs technology and Si.Finally, conclusions follow in Section V.

II. MULTI-SUBBAND MONTE CARLO MODELING
The Multi-Subband Monte Carlo (MSMC) simulator [22] employs a non-parabolic effective mass approximation (NP-EMA) energy model [23] for both quantization and transport.The MSMC simulator operates by dividing the device in a finite number of sections along the transport direction.In each section, the 1D Schrödinger equation is solved to obtain the subband profile.The subband occupation along the transport direction is computed by solving the Boltzmann Transport Equation (BTE) with the Monte Carlo method [24].In this way, far-from-equilibrium transport and quantization normal to the transport direction are accounted for.Interface traps have been introduced in the out-of-equilibrium solution of the coupled Schrödinger and Poisson equations as a sheet of charge at the interface between the channel and the gate dielectric, as reported in [25].MSMC simulations account for scattering mechanisms, such as elastic intravalley and inelastic intervalley phonons, remote phonons from the high-κ dielectric, local polar phonons, Coulomb, alloy, and surface roughness scattering [24].The schematic view of the simulated ultra-scaled DG-UTB structure is shown in Fig. 1.
The device considered in this work is a simplified template structure that resembles existing InGaAs technology including only HfO2 as the gate oxide [26].Other common device Fig. 2. a) DIT energy distribution employed in the MSMC simulations.The black solid curve is the model proposed in [13] to match the experimental data (green diamond and red square symbols) found in [19], [20], respectively, w/ WFP.The model is then modified to obtain the DIT (blue dashed line) to be used in the QDD and the MSMC w/o WFP.b), c) show the trapped charge density (NTRAP) and electron mobility (μn) vs the inversion charge density (NINV) with the two trap distribution [black solid (blue dashed) curve in a) used in the MSMC w/ WFP (w/o WFP)], showing that the proposed approach does not modify the electrostatic and transport behavior of the device even when the WFP in the gate oxide is not accounted for.realizations include a thin Al2O3 interfacial layer (~5-10 Å) between HfO2 and the semiconductor [27].The geometrical parameters are reported in the caption of Fig. 1, and were chosen starting from the semiconductor roadmap (ITRS) indications for Ge/III-V semiconductors [12], carefully adjusted to preserve electrostatic integrity in terms of subthreshold slope (SS) and drain-induced-barrier-lowering (DIBL).While MSMC simulations do not take into account possible SS deterioration due to SDT, full-quantum atomistic simulations showed limited VT-shift (due to SS degradation at given IOFF) for the DG-UTB devices under study [2].Theoretical studies have also shown that by properly reducing the body thickness and employing sufficiently long underlaps it is possible to downsize DG-UTB InGaAs MOSFETs to LG = 5 nm [28].These considerations point to the fact that the SDT in the device under study is not a major concern, allowing the successful scaling down to LG = 10.4 nm.The modeling of the device electrostatics with the inclusion of interface traps was carried out by: i) employing a DIT matching experimentally measured data; ii) preserving the device geometry, particularly by not increasing the channel thickness as done in previous works [21].The latter is a crucial point, since tCHAN strongly influences the variability of the device, especially at ultrashort LG [9].In other words, to avoid compromising the dependability of the variability analysis, unaltering tCHAN is mandatory.The reference MSMC simulation setup in this work is taken from [13].
Figure 2a) shows the calibrated distribution (black solid curve) [13], along with the experimental data (green diamond and red square symbols) [19], [20].The trap distribution in [13] was originally employed to reproduce mobility degradation and transfer-characteristic hysteresis of InGaAs planar devices (as discussed in [5]), and was calibrated on distributions measured on InGaAs MOS test structures [19], [20].While in general DIT depends on material properties and on process conditions (and thus it is possible to have different DIT for a given oxide/semiconductor interface) we chose this particular distribution because it is representative of actual InGaAs technology, satisfying the constraint i) discussed previously.To reproduce the MSMC results with the TCAD simulator, we employed a QDD model that considers both the increased confinement of carriers in the channel and the quasiballistic transport at very short channel length.The quantumcorrection is implemented by the Modified Local Density Approximation (MLDA) model, [29], that requires no calibration parameter.
Since the QDD, differently from the MSMC, does not consider the electron-Wave-Function Penetration (WFP) in the gate oxide (stemming from the strong geometric confinement due to thin tCHAN), the WFP was turned off in the MSMC as well [30].To maintain the same results as the MSMC w/ WFP, in the MSMC w/o WFP and QDD setups we employed a modified trap distribution model [blue dashed curve in Fig. 2a)].Such a distribution was obtained by translating the original model [black solid curve in Fig. 2a)] towards higher energies (compensating for the difference in the first available electron energy level that arises when not considering the WFP).This shift allowed recovering the same relationship between the trapped charge density in the channel (NTRAP) and the inversion charge density (NINV) as compared to that obtained with the MSMC simulations including the original trap distribution and WFP, as shown in Fig. 2b).Thus, the adopted systematic approach allowed preserving the electrostatic properties of the original device even without directly accounting for the WFP.In addition, the surface roughness parameters in the simulation w/o WFP were modified with respect to [13] to compensate for the different wave-function shapes that influence the scattering rates and the electron mobility (μn) [31].After the recalibration, similar μn-NINV to that of the original device w/ WFP was achieved, thus preserving the transport properties as shown in Fig. 2c).The unusual increase of the mobility with inversion charge density is caused by the wave function confinement effect in DG-UTB MOSFETs, which is not observed in single-gate devices (like the mobility reported in [13], obtained with the same surface roughness and Coulomb scattering as well as the same DIT profile used in this work).In fact, in the case of the DG-UTB MOSFET, the strong geometric confinement causes the device to operate in the quantum limit, with only the first subband of the conduction band being occupied.Thus, with increasing NINV, the Fermi Level penetrates more deeply into the subband (since the charge can only be supplied from this subband) and this in turn leads to an increase of the mobility, as already observed in [32], [33].

III. CALIBRATION OF QUANTUM DRIFT-DIFFUSION SIMULATIONS
In this section, we describe the systematic calibration procedure developed to correctly reproduce both the MSMC electrostatics and transport with the QDD setup.The TCAD simulator employed in this work to implement the QDD model is the commercial software SDevice TM [34].We employed the same trap distribution as the one used in the MSMC setup [shown in Fig. 2a), blue dashed curve] and calibrated the mobility vs carrier density curve in TCAD.The model employed to reproduce the MSMC mobility curve was the University of Bologna Model [35], available in SDevice TM [34].The calibration of the mobility model of the QDD vs MSMC was performed on a long-channel device (then used for the short-channel device) (LG = 100 nm) biased at low VDS (25 mV) to avoid influence of short-channel effects, quasiballistic transport and velocity-saturation effects.Besides the calibration of the mobility model, no further parameter adjustment was required to obtain the agreement between MSMC and QDD shown in Fig. 3.The agreement is obtained in terms of a) ID-VGS, b) NINV-VGS, c) NTRAP-VGS, and d) μn-NINV curves.The matching of the electrostatic and transport characteristic between MSMC and QDD was made possible by using the same DIT and mobility curve.This allowed ultimately to reproduce the ID-VGS curve, as shown in Fig. 3a).The residual discrepancy between MSMC and TCAD [in particular for the NINV-VGS curve, see Fig. 3b)] is due to the different quantization models employed by the simulators [30].In conclusion, the systematic calibration procedure adopted in this work guarantees that the QDD simulation results are consistent with the MSMC obtained with a trapdistribution model that matches the experimental data, thereby satisfying the two constraints defined in Section II.
The calibrated QDD setup was then used to simulate the ultra-scaled DG-UTB 10.4-nm device and to compare with the MSMC results obtained with the same device geometry.Results are shown in terms of ID-VGS curves (Fig. 4), for two different VDS biases (for the linear and saturation regimes, respectively).The same models used for calibration of the long channel device were used in this case (with the same parameter values) with the addition of an empirical ballistic mobility model and the Canali model accounting for velocity saturation effects, both available in SDevice TM [34].The empirical ballistic model provides an additional contribution to the mobility which is LG-dependent via a calibration Fig. 6.NTRAP vs NINV for the 15-nm (blue solid curve) and 10.4-nm (yellow dashed curve) devices.The channel thickness tCHAN is 7 nm and 4 nm, respectively.The NINV for the results in Fig. 5, i.e. at threshold condition, is indicated.The increase in trapped charge density for lower tCHAN is explained by the deeper penetration of the Fermi-level in the conduction band, thus probing the trap distribution where the trap density is higher, see Fig. 2a).parameter that was set in agreement with [36] to correctly reproduce transport in short-channel InGaAs devices.Note that the ION/IOFF ratio of the DG-UTB device under study is about 4 orders of magnitude (see Fig. 4), which is in line with ITRS requirements [12] as well as state-of-the-art InGaAs Tri-Gate devices on Si-substrates [27], with record value as high as ~2000-2500 (for LG as low as 13 nm).These remarks demonstrate that although the DG-UTB device in this work represents a simplified version of realistic technology, the variability analysis carried out can be considered to be relevant for current state-of-the-art InGaAs devices.

IV. VARIABILITY ANALYSIS
The calibrated 10.4-nm device was then used as a reference to assess the effect of random interface-trap concentration on the variability on VT.For brevity, we will refer to VT variability as the standard deviation of the threshold-voltage distribution, σ(VT).The 2D structure of Fig. 1 was protruded in the third dimension by 14 nm (i.e., the gate width) to obtain a 3D mesh for the variability analysis.SDevice TM incorporates the statistical Impedance Field Method (IFM) [10] as an efficient yet accurate tool to assess the impact of several variability sources independently of each other.The statistical IFM treats variability akin to small perturbations of the nominal device [i.e., in this case the device calibrated as in Fig. 4)] by calculating the altered response for a large number M of randomized device realizations (in our case, M = 10,000) as the linear response to the device perturbations via a Green's function-based approach [34].This is a simplified yet sufficiently accurate and efficient way of assessing variability, as the full (3D) QDD self-consistent device simulation needs to be solved only once.As variability sources, we considered all the relevant microscopic sources known for ultra-scaled MOSFETs [37], i.e.: RDF [14], WFF [15], BLER, and GLER [8].In addition to these sources, we included BGF [16] and ITF.The modeling parameters adopted for WFF, BGF, B/G-LER are summarized in Table I (more details on the implementation of the randomized distribution for each source are provided in [9], [16]).The dependability of the variability analysis based on the IFM was verified in [9] by matching Si σ(VT) experimental data, due to the lack of the same for InGaAs devices (for statistically meaningful datasets).
BGF stems from the random variations of indium content (i.e., mole fraction) in In0.53Ga0.47Aswhich cause the channel volume to be subject to random variations in the bandgap.BGF is modelled following the approach adopted in [16] with parameters as shown in Table I.ITF reflects the random number of traps present at the interface between the gate oxide and the channel, in a similar way to the discrete random dopants in the semiconductor.Therefore, when constructing the M device samples, at each mesh vertex along the interface, the random number of traps is calculated from a Poisson distribution with an average equal to the nominal number of traps determined from the DIT (shown in Fig. 2a).For the given trap distribution and gate area, we can estimate the (occupied) trap number to span from about 5 to 21 (depending on the position of the Fermi level).We considered the traps to be uniformly distributed (on average), as previous results on similar III-V DG MOSFETs showed that the influence of random single-trap position along the gate interface is negligible [38].Since with IFM the self-consistent QDD solution is computed only once, the trap filling ratio is obtained from the reference solution at each bias point, and device characteristic variations are obtained with the linearized method discussed previously.This is a simplified approach with respect to more complex atomistic simulations, that however require much higher computational effort compared to IFM.
The results of the analysis in terms of σ(VT) are shown in Fig. 5. Figure 5a) shows a comparison between the σ(VT) of the 10.4-nm and the 15-nm device.Variability results for the 15-nm device were calculated from QDD simulations calibrated on MSMC with an effective DIT obtained from the model of Fig. 2a) (black solid curve).The effective distribution was obtained following the same procedure as that described in Section II for the 10.4-nm device, to preserve the NTRAP vs NINV relationship (results not shown for brevity).From Fig. 5a), it can be seen that, upon scaling, both RDFand WFF-induced σ(VT) increase, BLER and GLER decrease (due to reduction of the associated amplitude, Δrms, following ITRS, see [9] and Tab.I) and BGF shows a negligible variation.Notably, ITF-induced σ(VT) has a ~6× increase, negatively impacting the total VT variations.This increase is a consequence of the higher trapped charge density for the scaled device, as shown in Fig. 6.The plot compares NTRAP vs NINV for the 15-nm (blue solid curve) and 10.4-nm (yellow dashed curve) devices.Since the interface traps are Poissondistributed, if their mean value increases (proportional to NTRAP) then also the standard deviation does, thus explaining the ITF increment shown in Fig. 5a) [14], [17].The ITF trend is more clearly shown in Fig. 5b), where the σ(VT) for the 10.4-nm device for each source is normalized to that of the respective source for the 15-nm device.These results indicate that scaling strongly worsens ITF.Similar trends of increased trap-induced variability due to higher trapped charge were found also for Si MG-MOSFETs [14], [17], [18].However, conversely to InGaAs, in Si devices the increased NTRAP was attributed to the effects of aging [14], [18] rather than to Fig. 7. Comparison of the scaling behavior of total VT variability, σ(VT), for InGaAs with-(purple diamonds) and without-(yellow squares), from [16], interface traps, Silicon Intel Data (blue dots), from [39], and Si QDD simulations (orange star), [9].increased quantum confinement (which is stronger in InGaAs due to its low effective mass).Stress-induced trap generation is expected to take place in InGaAs devices as well, but it is out of the scope of the present work.
The effect of interface traps on the σ(VT) induced by all other variability sources (i.e., other than ITF) can be appreciated with the aid of Fig. 5c).It shows the σ(VT) for both the 15-and 10.4-nm devices normalized to the σ(VT) obtained for the same devices without interface traps.(The reference devices without interface traps were calibrated to MSMC simulations as well, as reported in [16]).Remarkably, for both nodes, the other variability sources appear not to be significantly affected by the presence of interface traps, except for BLER.This result indicates that the device with interface traps is more sensitive to BLER, especially at the 10.4-nm node.This is clear from the fact that electrostatic integrity is reduced by the presence of traps, and, since BLER acts as a random variation of the channel thickness, the VT fluctuations increase for the trap-affected devices.
The increase of ITF-induced σ(VT) also impacts the total σ(VT) calculated as the quadrature sum of the contribution of all the different sources, assuming each source to be independent of each other (similar to the approach adopted in our previous work [9]).This is shown in Fig. 7, along with data obtained from our previous work without considering interface traps [16] and data for Si devices, from both an existing technology [39] and our results [9].The comparison shows that InGaAs variability is higher than the latest reported from Intel regarding Si (at the 14nm node) [39], and that is further increased when considering interface traps.Moreover, the scaling of the InGaAs technology further increases the total σ(VT), thereby contrasting the scaling trend of improved performance with reduced dimensions observed in Si technology.This result indicates that the significant increase of variability due to interface traps could be a serious bottleneck for the adoption of InGaAs for ultra-scaled nodes for general purpose digital applications.

V. CONCLUSIONS
We presented a systematic modeling approach to evaluate in TCAD the effects of interface traps electrostatics, transport and in DG-UTB III-V MOSFETs.Moreover, we assessed the impact of random interface-trap concentration on the statistical variability of the threshold voltage (VT) via quantum-corrected drift-diffusion (QDD) simulations calibrated on MSMC results.The systematic modeling approach adopted in this work allowed reproducing a full set of MSMC electrostatic and transport results with QDD simulations by employing the same DIT distribution (obtained from experimental data) and by calibrating the mobility curve.This approach was instrumental to achieve agreement between MSMC and QDD results without altering key geometrical parameters that would compromise the variability analysis.Moreover, our approach is applicable in other extremely scaled III-V devices where experimental data is lacking and comparison between TCAD and more sophisticated simulators is required.From the variability analysis we found that although the most detrimental variability source is the Work-Function Fluctuation (WFF), the contribution of Interface-Trap Fluctuation (ITF) to VT variability increases significantly when scaling the device dimensions.This is due to the stronger confinement that shifts the Fermi level towards higher energies and thus increases the trapped-charge density.The significant ITF impact on the total VT variability contrasts the trend of reduced variability with smaller dimensions, as opposite to Si devices.Thus, we conclude that ITF could be a serious bottleneck for InGaAs technology at ultra-scaled nodes for general-purpose digital applications.

Fig. 1 .
Fig. 1.Schematic view of the simulated Dual Gate -Ultra Thin Body (DG-UTB) device.The geometrical parameters are: LG = 10.4 nm, tCHAN = 4 nm, tOX = 3.3 nm, tVOL,G = 3 nm, LSD = 22 nm and LUND = 2 nm.DIT indicates the presence of the trap distribution at the interfaces between the channel and the gate oxide.The same parameter set was used for the long-channel device with LG = 100 nm.

Fig. 4 .
Fig. 4. ID-VGS calibration of the QDD (orange solid and black dashed curves) over MSMC (blue square symbols) simulations for the ultra-scaled reference device (LG = 10.4 nm) used in the variability analysis in the linear and saturation regimes.
Fig. 5. VT variations, σ(VT), induced by the six variability sources considered in this work.a) Comparison between the σ(VT) calculated from devices with LG = 15 nm (blue bins) and LG = 10.4 nm (yellow bins).b) σ(VT) for the 10.4-nm device normalized to the 15-nm device.Red (blue) bins are the variability sources that worsen (improve) with scaling [i.e., increase (reduce) the induced σ(VT)].c) σ(VT) for both 15-and 10.4-nm devices normalized to the one obtained for devices with the same LG (respectively) but without interface traps.