A Novel Program-Verify Algorithm for Multi-Bit Operation in HfO2 RRAM

In this letter, we propose a dispersion-aware program-verify algorithm to enable reliable multi-bit operations in HfO2-based RRAM. The significant intrinsic dispersion of the resistive states, typically hindering multi-bit operations, is exploited to devise a program-verify scheme which enables the multi-bit operations with unique properties of failure resilience and adaptability to degradation. We show that an appropriate choice of the algorithm parameters can minimize the average number of cycles needed to program the cell, enabling fast and reliable multi-bit operation. This maximizes the bit/cell ratio and minimizes the dispersion of targeted resistive states.


I. INTRODUCTION ESISTIVE Random Access Memory (RRAM) based on
HfO 2 allows fast low-power operation, and high-density [1][2], becoming a promising alternative non-volatile memory.Still, inherent stochastic features, i.e. randomness in the switching mechanism [3][4][5], hamper multi-bit operations.Major concerns are cycling variability [3][4], i.e. considerable dispersion of High-Resistive (HRS) and Low-Resistive State (LRS) resistances, and resistance distributions degradation [6], i.e. changes in the stochastic response of the device over time.Controlling these phenomena, reducing RRAM reliability, requires employing program-verify (PV) schemes.In this letter, we propose a dispersion-aware PV (DAPV) scheme to minimize resistance dispersion and achieve reliable multi-bit operation.PV schemes for HfO 2 RRAMs reported in the literature, though efficient, are not tailored to prevent device failures [7][8][9][10].Also, they are not designed to handle resistance distribution degradations.The proposed algorithm exploits the stochastic response of RRAM to the reset operation and the possibility of controlling the average HRS resistance via the reset pulse voltage to achieve unique properties of resilience to failures [11] and adaptability to degradation.The DAPV scheme enables 2 bit-cell operation, with better reliability compared to classical schemes [7][8][9][10].
Christian Wenger is with IHP GmbH -Leibniz institute for innovative microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany.configuration -devices details are reported elsewhere [12].The access nMOS is used to enforce a current compliance, I C , to prevent current overshoot [13].The preliminary forming operation is performed with I C ranging from 50µA to 100µA by applying a DC voltage sweep up to 3.5V (not shown).Forming results in the creation of a Conductive Filament (CF) [3][4][5].Then, we perform 50 complete pulsed switching cycles (set and reset), and we repeat the experiment for different reset conditions.The reset operation, driving the device in HRS, is performed by applying a negative voltage pulse (-V RESET ), resulting in a partial oxidation of the CF (creation of a dielectric barrier) [3][4][5].The set operation, driving the device in LRS, is performed by applying a 2V pulse, and leads to the restoration of the CF [3][4][5].The RRAM resistance, R, is measured after each operation by applying a V READ =100mV pulse.Set, reset, and read pulses are all 10μs wide, including 2μs of rise/fall times.The total pulse period is 20μs.

III. THE PROGRAM-VERIFY ALGORITHM
Figure 1 shows the probability distributions of both LRS and HRS resistances over 50 complete switching cycles when three different V RESET are applied, namely 1.3V, 1.5V and 1.8V.The LRS resistance (R LRS ≈9kΩ) is normally distributed with no dependence on V RESET , consistently with previous results and other studies [3][4][5]11].Conversely, the HRS resistance, R HRS , is log-normally distributed [3][4] and strongly depends on V RESET , resulting in a significant R HRS dispersion.The unambiguous identification of the device state after each set/reset operation requires no overlap between the tails of the R LRS and R HRS distributions across the whole memory lifetime.Hence, a correct monitor of the device reliability is the worst- case read window (R HRS,MIN /R LRS,MAX ), much lower than the median read window (R HRS,50% /R LRS,50% ) due to R HRS dispersion, see the inset in Fig. 1.As such, the device shows reliable switching as, regardless of V RESET , the R LRS and R HRS distributions are never overlapped, Fig. 1.Unfortunately, the R HRS distributions related to the three different V RESET are mostly overlapped.This hinders multi-bit operation, which can be achieved only by applying PV schemes [7][8][9][10].
Typically, it consists in delivering to the device a train of pulses with incrementally higher voltage or pulse width during reset (program), until the desired R level (verify) is reached [7][8][9][10].In general, if the desired condition is not met within 20 pulses the algorithm fails [7][8][9][10].However, this procedure cannot be reliably applied to TiN/Ti/HfO 2 /TiN RRAM, since it may induce failures.Indeed, the first reset pulse creates a dielectric barrier within the CF [3][4][5].The high electric field given by the following pulse may lead to the barrier disruption ("negative set failure") [11], rather than to an R HRS increase.This failure mode occurs when the reset operation is performed on a device which is already in HRS.This scenario is associated with two competing physical mechanisms: 1) the further growth of the dielectric barrier within the CF and 2) the breakdown of the barrier due to the applied electric field.So, the application of consecutive reset pulses may cause the device to fail.Hence, different strategies have to be devised to achieve "negative set failure" resilience.

A. Unconstrained Program-Verify (UPV)
A straightforward method to target a tight R HRS distribution (from R MIN to R MAX ) while avoiding the "negative set failure" would be the following: 1. Choose V RESET and a target R span (R MIN -R MAX ) 2. Reset the device 3. Check if the resistance, R, is R MIN <R<R MAX 4. If not, apply a set pulse and go back to 2 Notably, in classical schemes the set pulse is applied only when R>R MAX [7][8][9][10], whereas another reset pulse is applied if R<R MIN .Here, instead, a set pulse is applied every time the programmed R value is out of the target R span.This approach is more time-consuming due to the additional set pulse but circumvents the "negative set failure".However it requires an accurate matching between the applied V RESET and the selected R span.For instance, Fig. 1 suggests it is unlikely to achieve 10 5 Ω<R<2•10 5 Ω when V RESET =1.3V.This choice will imply the algorithm failure (missing the target R span within 20 cycles).So, the algorithm parameters (V RESET , R MIN , and R MAX ) must be wisely chosen to guarantee success and to minimize total programming time: with n being the number of cycles, T RESET (T SET ) the reset (set) pulse period and T CHECK the time to verify if R is within the targeted R span.However, if the R HRS distribution changes during device operation [6], even a good initial choice of the parameters may cause the algorithm to fail.As such, this scheme is resilient to the "negative set failure" but shows no adaptability to degradation.

B. Dispersion-Aware Program-Verify (DAPV)
A more robust approach is based on the real-time estimation of the most appropriate V RESET for the targeted R span.Indeed the R span which can in fact be targeted in the reset operation depends on V RESET , Fig. 1.If the algorithm misses the target R span by always exceeding (falling behind) it, then reducing (increasing) V RESET is required to achieve the target R span.The proposed scheme is summarized in the flow chart in Fig. 2. The counter "Iter" tracks the number of cycles, while "CountU" and "CountD" track how many consecutive times the programmed R exceeds (falls behind) the target R span.After each program operation (set and reset) and R evaluation, this scheme checks if V RESET must be changed for the next iteration.To this point, either CountU or CountD is compared to its maximum value, which is a parameter of the algorithm as well as the initial V RESET , R MIN , R MAX , and the maximum number of cycles Iter MAX (typically 20).Moreover, we also set  boundaries on V RESET to prevent over-reset and under-reset failures (V RESET,MIN =1.3V, V RESET,MAX =1.8V) [11].The DAPV scheme allows optimizing the reset conditions according to the actual device statistical response [3][4][5], showing adaptability to R HRS distributions degradation [6].

IV. DISCUSSION
The proposed algorithm is tested 100 times with different input parameters combinations, targeting three different R spans.R MIN , R MAX and initial V RESET values for each target R span are reported in Fig. 3.The remaining parameters are fixed at CountU MAX =CountD MAX =3 (chosen to minimize the average number of cycles required to program the device -not shown) and Iter MAX =20.Resistance distributions are reported in Fig. 3 showing the superior control of the final resistance dispersion.Fig. 4 shows the performance metric of the DAPV.The algorithm always succeeds in < 10 cycles, and performs better for larger R HRS target spans, as expected.This confirms the possibility of reliable two-bits/cell operation with no failures.Similar performances are obtained on 10 different devices, as reported in the inset of Fig. 4. Notably, the user can freely define the number of target R spans and their boundaries (distributions margins), trading-off between the number of bits/cell and algorithm performance.Compared to UPV, DAPV offers much better performance.Fig. 5 indicates that DAPV can program a cell in < 10 cycles with no failures, while UPV failure rate in the same conditions is 32%.Also, DAPV has a better success rate at low cycles than UPV, which reduces the possible endurance degradation resulting from the application of program-verify schemes.So, though being computationally heavier than UPV due to higher complexity (compared to UPV, two comparisons per cycle are added, Fig. 2), the DAPV shows lower average programming time.

V. CONCLUSIONS
We proposed a new dispersion-aware program-verify algorithm for HfO 2 RRAM.It exploits the intrinsically stochastic response of RRAMs to achieve an optimal control of resistance values.It allows reliable multi-bit operation with no failures and optimized programming time, while displaying the unique properties of failure resilience and adaptability to degradation.3).Regardless the target R span, DAPV succeeds in < 10 cycles and shows no failures achieving two bits/cell operation.The table (inset) reports the median number of iterations needed for DAPV to succeed for the device under test and the same value averaged over 10 devices tested in the same conditions.

AFigure 1 .
Figure 1.RLRS and RHRS distributions for three different VRESET.IC is 100μA.Only RHRS distribution depends on VRESET.The colored and black vertical dashed lines represent the minimum of each RHRS distribution and the maximum RLRS, respectively.The worst-case read window is indicated by an arrow for each VRESET.In the inset, the worst-case (red squares) and the median (blue circles) read window vs. VRESET.

Figure 3 .
Figure 3. RLRS and three RHRS distributions for 100 cycles as obtained with DAPV.For each target R span, the initial VRESET is varied by the algorithm to ensure successful writing and minimal programming time.The table reports the initial VRESET for the three target RHRS span, along with the median and average values over 100 algorithm runs of the effective VRESET which is used by the algorithm when succeeding in programming.The other parameters are set to IterMAX=20, CountUMAX=CountDMAX=3.

Figure 2 .
Figure 2. Flow chart of the proposed DAPV algorithm.The algorithm parameters are IterMAX, CountUMAX, CountDMAX and the initial VRESET.Orange boxes are comparison operation.Notably, only two comparisons per cycle are added, compared to the UPV.

Figure 4 .
Figure 4. DAPV performance evaluated on a device formed with IC=100μA (R distributions in Fig.3).Regardless the target R span, DAPV succeeds in < 10 cycles and shows no failures achieving two bits/cell operation.The table (inset) reports the median number of iterations needed for DAPV to succeed for the device under test and the same value averaged over 10 devices tested in the same conditions.